During the manufacture of semiconductor memories, such as a synchronous dynamic random access memories (“SDRAMs”), it is necessary to test each memory to ensure it is operating properly. Electronic and computer systems containing semiconductor memories also normally test the memories when power is initially applied to the system. A typical SDRAM includes a number of arrays, each array including a number of memory cells arranged in rows and columns. During testing of the SDRAM, each memory cell must be tested to ensure it is operating properly. In a typical prior art test method, data having a first binary value (e.g., a “1”) is written to and read from all memory cells in the arrays, and thereafter data having a different binary value (e.g., a “0”) is typically written to and read from the memory cells. A memory cell is determined to be defective when the data written to the memory cell does not equal that read from the memory cell. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern “101010 . . . 0” written to the memory cells in each row of the arrays.
In a typical test configuration, an automated memory tester is coupled to address, data, and control buses of the SDRAM, and applies signals to these buses to perform the desired tests. As the storage capacity of SDRAM and other memory devices increase, the number of memory cells and hence the number of data transfer operations the tester must perform correspondingly increases. For example, in a memory array having n rows and m columns of memory cells, the tester performs n*m cell accesses in writing the first binary data values to all the memory cells in the array, and thereafter performs n*m cell accesses in reading the same data. The tester must once again perform n*m accesses in writing data having a second binary value to each memory cell, and the same number of accesses in reading this data. The tester thus performs a total of four times n*m cell accesses, each of which requires a bus cycle to perform.
As the tester reads data that has been written to each address of the memory device being tested, the tester compares each bit of the read data to the corresponding bit of the data that was written to that address. Any discrepancy in each comparison is recorded as a bit error for that cell, and the collection of bit errors is referred to as error data. The bit errors are generally stored in a high-speed memory, known as an Error Catch RAM (“ECR”), in real time at the rate the bit errors are generated. However, there are at least two problems with this approach. First, the storage capacity of the ECR must be commensurate with the storage capacity of the memory device being tested. Yet high capacity memory devices capable of operating at a sufficiently high speed are very expensive. One approach is to use an expensive high-speed static random access memory (“SRAM”) device, which is capable of capturing the fail data from the memory device at the required operating speed. The other approach is to use interleaved banks of DRAM to capture the fail data. Interleaving pages of DRAM can be less expensive than using a high-speed SDRAM device, but poses additional complications in reconstructing the fail data. The difficulty in using either of these approaches is exacerbated by memory devices having significantly greater storage capacities, such as state-of-the-art NAND Flash memory devices. As a result, conventional testers must separately test different portions of such high-capacity memory devices, which requires a significant amount of time to complete a test.
The second problem with conventional ECR techniques is the length of time required to complete a test and use the test results to calculate a repair solution for the memory device being tested. Specifically, once the fail data have been captured by the ECR, the ECR must be scanned to read the fail data. A computer or other device used in the test system must then process the fail data to determine how the memory device being tested should be repaired by substituting redundant rows, columns or blocks of memory cells for rows, columns and blocks, respectively, of memory cells found to be defective. It can require a considerable period of time for the test system to read the ECR and then process the fail data, thereby slowing the throughput of the testing system.
There is therefore a need for a testing system and method that can capture and process fail data in read time as data bits are being read from a memory device being tested so that a repair solution for the memory device will be available almost as soon as the fail data capture has been completed.